Carry save adders are often employed in high-speed multipliers, where they generally are able to function more rapidly than “carry propagate” or “ripple carry” adders. A carry save adder is distinguished from other types of adders by the fact that the “carry bits” and half-sum bits (hereinafter referred to simply as “sum bits” for convenience), which result from each addition, are not immediately combined or consolidated but instead are saved separately from each other for subsequent use in the next addition to be performed by the next cascaded carry save adder.
Because a carry save adder does not completely perform the relatively time-consuming process of combining carries with sum bits between successive additions in the multiplication process but instead defers this task until the final cycle of the multiplying operation, they are faster than ripple carry adders.
Typically, carry save adders have multiple inputs, e.g., three inputs, designed to receive multiple numbers, e.g., three numbers, to be added and have two outputs, designated as “sum” and “carry.” An example of such a carry save adder is illustrated in FIG. 1. FIG. 1 illustrates what is referred to as a multiple stage “4-to-2” carry save adder 100 that includes multiple carry save adders 101A-B cascaded together. Carry save adders may often be cascaded together where each cascaded carry save adder may be referred to as a cell or stage.
Referring to FIG. 1, as stated above, a multiple stage 4-to-2 carry save adder 100 may include 4-to-2 carry save adders 101A, 101B. 4-to-2 carry save adders 101A, 101B may collectively or individually be referred to as 4-to-2 carry save adders 101 or 4-to-2 carry save adder 101, respectively. 4-to-2 carry save adders 101A, 101B may include full adders 102A-B, 102C-D, respectively, that each receive three inputs and output a carry and a sum bit. Full adders 102 A-D may collectively or individually be referred to as full adders 102 or full adder 102, respectively. Full adders 102A, 102C may be referred to as the lower order full adder or carry save adder. Full adders 102B, 102D may be referred to as the higher order full adder or carry save adder.
Referring to FIG. 1, full adder 102A of 4-to-2 carry save adder 101A may receive three inputs, designated as A, B and C. Full adder 102A may output a carry and a sum bit, designated as C′out and Sum′. The output, Sum′, may be input to the following full adder 102, full adder 102B, of 4-to-2 carry save adder 101A. Full adder 102B may also receive the inputs designated as D and C′in. The carry C′in may refer to the carry out bit, C′″out, generated by carry save adder 101B (lower order full adder 102C) in the previous stage or stage (next lower order bit). Full adder 102B may output a carry bit and a sum bit, designated as C″out and Sum″, respectively.
4-to-2 carry save adder 101B may be configured similarly as 4-to-2 carry save adder 101A. Full adder 102C may receive inputs A′, B′ and C′ and outputting outputs C′″out and Sum′″. The output, Sum′″, may be inputted to full adder 102D. Full adder 102D may also receive inputs D′ and C′″in where C′″in may refer to the carry out bit generated by the 4-to-2 carry save adder (lower order full adder) in the previous stage or stage (next lower order bit). Full adder 102D may output a carry bit and a sum bit, designated as C″″out and Sum″″.
As illustrated in FIG. 1, the input, C′in, to full adder 102B was generated from full adder 102C of 4-to-2 carry save adder 101B located in the previous stage. Since the signal, C′in, is generated from the previous stage, it takes time to propagate to the current stage and input into full adder 102B of 4-to-2 carry save adder 101A. Due to the propagation delay of signals generated from previous stages, such as signal C′in, the outputs generated by carry save adders, such as full adder 102B, are delayed. Hence, there is a need in the art to reduce the delay in outputting the sum and carry bits.
Carry save adders, such as 4-to-2 carry save adders, have been typically built using static logic such as pass transistors and multiplexers. Dynamic logic, on the other hand, has the advantage in both speed and area consumed on the chip over static logic. However, dynamic logic dissipates power even when the input signal states are unchanged.
Additionally, dynamic logic may be implemented in a dual rail embodiment in which all of the logic is duplicated, one gate for each sense of the data. That is, each logic element includes a gate to produce the output signal, and an additional gate to produce its complement. Such implementations may exacerbate the power dissipation in dynamic logic elements, as well as obviate the area advantages of dynamic logic embodiments.
Limited switching dynamic logic (LSDL) produce circuits which mitigate the dynamic switching factor of dynamic logic gates with the addition of static logic devices which serve to isolate the dynamic node from the output node. Additional details regarding LSDL circuits are described in U.S. patent application Ser. No. 10/116,612, filed on Apr. 4, 2002, entitled “Circuits and Systems for Limited Switch Dynamic Logic,” which is hereby incorporated herein by reference in its entirety. Additionally, LSDL circuits and systems maintain the area advantage of dynamic logic over static circuits, and further provide both logic senses, that is, the output value and its complement. Hence, it would be desirable to implement LSDL in carry save adders.
Therefore, there is a need in the art to build carry save adders using LSDL technology to use the lowest amount of area while reducing power consumption and improving speed such as by decreasing the delay of outputting the sum and carry bits.